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Reference -P/N: 12012003
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1,089.00€ Exclu. VAT

FASTCOM GFSCC synchronous communication cards RS422 / RS485

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Fastcom: GFSCC
synchronous communication cards RS422 / RS485

Designed to comply with the latest PCI specifications, the Fastcom: GFSCC Universal PCI (PCI version 2.3) adapter will operate in both 5V and 3.3V PCI slots. This means the card will work in the high speed PCI-X slots commonly found in most new servers, as well as the standard PCI slots in desktop PC’s. This flexibility allows for a single serial interface board to be used across a wide range of different types of computers including both current and future computing systems. The Fastcom: GFSCC adapter is the one of the most advanced synchronous communications adapters in the industry. The Fastcom: GFSCC supports data rates up to 20 Mbit/s. The Fastcom: GFSCC is a dual channel adapter, with each one being individually configurable to use HDLC/SDLC, ASYNC (using 16C950 UARTS), orFastcom®: X-Sync protocols. Although similar to the ESCC and SuperFastcom families of adapters, the GFSCC expands on our previous adapters. The most notable expansion is the longevity of the components of the board. Faced with the inevitability of obsolescence, Commtech decided to put an end to the lifespan problems that plague most computing customers. We designed a serial communications controller with our customers’ needs in mind, and built a card around it. Wholly designed and owned by Commtech, Inc, this FPGA based SCC has most of the features that you are used to seeing in a quality Fastcom product. It also includes a few new features that come directly from customer requests. If the existing FPGA technology is ever discontinued by the chip manufacturer, the design can simply be re-targeted to the next generation of FPGA chip with no impact on compatibility.

Difference Between Fastcom: GFSCC and Fastcom: GSuperFSCC
The GSuperFSCC card features bus-mastering DMA; therefore, it greatly decreases the amount of interrupts that must be serviced by the host CPU, thus freeing it up for other activities. By utilizing this DMA, the GSuperFSCC is able to stream gapless, full duplex data at the full 50 Mbit/s1. The standard GFSCC card is only able to perform the same task at around 20 Mbit/s. The standard card is capable of operating at rates up to 50 Mbit/s with data bursts. It cannot sustain higher rates without generating gaps in the data (e.g. idle between frames).

RoHS 3 2015/863/EU Compliant
CONNECTOR CONFIGURATION: Cable assembly (2 ft.) – HDDB62 plug to two DB25 plugs
BAUD RANGE: Using the user independent programmable clock generator in conjunction with the baud rate register, virtually any baud rate from 1 bps to 20 Mbit/s can be attained.
Maximum data rates are estimates. They are greatly affected by a number of different factors. See the data rates section of the manual for more details. This is possible as long as the operating parameters are within reason. If you have any question about whether the card can meet your needs, please contact Technical Support.
POWER REQUIREMENTS: +5V @ 450mA (typical)
Operating Temperature Range: 0 to 70 C
Humidity: 0 to 90% (non-condensing)
Half-length full-height
Height: 4.2″ (107 mm)
Length: 4.7″ (119.91 mm)
Weight: .2 lbs (90.719 g)


Never Obsolete
Customizable Firmware: The firmware for our GFSCC and GSuperFSCC product lines is fully-customizable. If you have a feature requirement you do not see listed, please contact us about modifying our firmware to meet your specific needs.
High speed: Up to 20 Mbit/s
Drivers: RS422 / RS485 multi-drop
True-Async mode. Each port can be set to use the on-board 16C950 UARTs and can be used as a standard serial (COM) port.
Automatic RS-485 handling
Transmit and Receive status LED’s for each port.
On board RS-485 termination network for each receive signal pair
Two independent full duplex serial channels
Data clocking mechanism independently selectable per channel per direction
Externally generated Rx and Tx clocks
Internally generated Rx and Tx clocks
On chip DPLL clock recovery
Independent baud rate generators
RxFIFO = 8KB per port (non-uart modes)
TxFIFO = 4KB per port (non-uart modes)
Programmable interrupt trigger levels (watermark)
Data protocols
The GFSCC and GSuperFSCC families of cards fully supports the HDLC framing convention. It does not support automatically decoding of the SDLC control fields. If control bytes are present in received frames they will be passed to the user as if they were part of the info field. If control bytes are required to be transmitted they will have to be generated by the user and written as if they were data.
Automatic flag detection and transmission
General frame format: 0x7e,info,CRC,CRC,[CRC,CRC,]0x7e
Frame format with maskable address enabled: 0x7e,address,[address,]info,CRC,CRC,[CRC,CRC,]0x7e
Zero insertion/deletion
One insertion/deletion
Shared flag mode: opening flag and closing flag of back-to-back frames can use the same flag.
Error detection (abort, overrun, underrun, CRC error, too long/short frame)
Can use CRC8, CRC-CCITT, or CRC32
Arbitrary Sync Sequence (Fastcom®: X-Sync)
Any begin/end frame sync sequence of up to 4 bytes
Frame format: SYN1,[SYN2,SYN3,SYN4,]info,[CRC,CRC, CRC,CRC,][TCR1,TCR2,TCR3,TCR4]
Maskable: can select all or parts of the sync sequence to be a sync match
Termination sequence detection up to 4 bytes (maskable)
Shared flag mode: opening flag and closing flag of back-to-back frames can use the same flag.
Error detection
Can use any of the available CRC methods
Transparent Mode
Fully bit transparent (no framing or bit manipulation)
Can synchronize using selectable frame sync signals
Data encoding schemes:
NRZ, NRZI, FM0/FM1, Manchester, Differential Manchester
Selectable frame sync signals
Pulse width of one clock at first bit of data
Pulse width of one clock at last bit of data
Pulse width of the entire frame
Optionally insert a variable number of clock cycles between data and FSS
Selectable polarity
Optional data flow control using modem control lines (RTS, CTS)
Programmable 8-bit preamble and postamble with selectable repetition rate (1 to 255 repetitions)
Data can be oriented as selectable MSB first or LSB first
Interframe time fill: idle as repetitive 1’s, flags, or sync sequences
CRC Support
Automatic handling in the transmit/receive direction
CRC-CCITT (also known as CRC16-ITU) (HDLC), CRC32 (HDLC), CRC16, CRC8 (HDLC)
Transparent CRC option
Reset as 0’s / 1’s
Continuous transmission of 1 to 4096 bytes
Selectable data rates
Synchronous (internally clocked) data rates up to 20 Mbit/s
Synchronous (externally clocked) data rates up to 20 Mbit/s
Asynchronous (DPLL clock recovery) data rates up to 12.5 Mbit/s
These maximum data rates are estimates. They are greatly affected by a number of different factors. See the data rates section of the manual for more details.
Data and clock inversion
Interruptible hardware timer
Transmit a single frame on the expiration of the hardware timer
Transmit a single frame on the detection of external signal
Included Libraries:
Network Analyzer
Cable, documentation, and software drivers included

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